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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES6111/D Rev 1, 05/2002
Low Voltage 2.5/3.3V Differential ECL/PECL/HSTL Fanout Buffer
The Motorola MC100ES6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.
MC100ES6111
LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT DRIVER
Freescale Semiconductor, Inc...
* * * * * * * * * * *
1:10 differential clock distribution 35 ps maximum device skew Fully differential architecture from input to all outputs SiGe:C technology supports near-zero output skew Supports DC to 2.7 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3V, -3.3V, 2.5V or -2.5V supply Standard 32 lead LQFP package Industrial temperature range Pin and function compatible to the MC100EP111
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Functional Description The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7 GHz. The device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts HSTL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6111 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6111 supports positive (PECL) and negative (ECL) supplies. The MC100ES6111 is pin and function compatible to the MC100EP111.
(c) Motorola, Inc. 2002
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MC100ES6111
Q3 Q3 Q4 Q4 Q5 Q5 Q6 18 Q6 17 16 15 14 13 VCC Q7 Q7 Q8 Q8 Q9 Q9 VCC 12 11 10 9 1 2 3 4 5 6 7 8 VEE
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 0 1 Q4 Q4 Q5 Q5
VCC
24 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28
23
22
21
20
19
VCC
CLKA CLKA
MC100ES6111
29 30 31 32
Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9
CLKB CLKB
Freescale Semiconductor, Inc...
CLK_SEL
VBB
CLK_SEL
VCC
CLKA
CLKA
CLKB 1
Figure 1. MC100ES6111 Logic Diagram Table 1. PIN CONFIGURATION
Pin CLKA, CLKA CLKB, CLKB CLK_SEL Q[0-9], Q[0-9] VEEa VCC I/O Input Input Input Output Supply Supply Type ECL/PECL HSTL ECL/PECL ECL/PECL
Figure 2. 32-Lead Package Pinout (Top View)
Function Differential reference clock signal input Alternative differential reference clock signal input Active clock input select Differential clock outputs Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation.
VBB Output DC Reference voltage output for single ended ECL or PECL operation a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC).
Table 2. FUNCTION TABLE
Control CLK_SEL Default 0 0 CLKA, CLKA input pair is active. CLKA can be driven by ECL or PECL compatible signals. CLKB, CLKB input pair is active. CLKB can be driven by HSTL compatible signals.
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CLKB
VBB
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Table 3. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
TFunc Functional temperature range TA = -40 TJ = +110 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 4. General Specifications
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Symbol VTT MM HBM CDM LU CIN JA
Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up immunity Thermal resistance junction to ambient JESD 51-3, single layer test board
Min 200 4000 2000 200
Typ VCC - 2a
Max
Unit V V V V mA
Condition
4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3
pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1
JESD 51-6, 2S2P multilayer test board
JC TJ
Thermal resistance junction to case Operating junction temperatureb (continuous operation) MTBF = 9.1 years
110
C
a. Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase b. Operating junction temperature impacts device life time. Maximum continues operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
TIMING SOLUTIONS
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MC100ES6111
Table 5. PECL/HSTL DC Characteristics (VCC = 2.5V 5% or VCC = 3.3V5%, VEE = GND, TJ = 0C to + 110C)
Symbol Control input CLK_SEL VIL VIH IIN Input voltage low Input voltage high Input Currenta VCC - 1.810 VCC - 1.165 VCC - 1.475 VCC - 0.880 100 V V A VIN = VIL or VIN = VIH Differential operation Differential operation VIN = VIL or VIN = VIH Characteristics Min Typ Max Unit Condition
Clock input pair CLKA, CLKA (PECL differential signals) VPP Differential input voltageb VCMR IIN Differential cross point voltagec Input Currenta
0.1 1.0
1.3 VCC - 0.3 100
V V A
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Clock input pair CLKB, CLKB (HSTL differential signals) VDIF Differential input voltaged VCC = 3.3V VCC = 2.5V VX Differential cross point voltagee IIN VOH VOL Input Current PECL clock outputs (Q0-9, Q0-9) Output High Voltage Output Low Voltage VCC = 3.3V5% VCC = 2.5V5%
0.4 0.4 0.68 0.9 200
V V V A VIN = VX 0.2V IOH = -30 mAf IOL = -5 mAf
VCC-1.2 VCC-1.9 VCC-1.9
VCC-1.005 VCC-1.705 VCC-1.705
VCC-0.7 VCC-1.5 VCC-1.3 100
V V
Supply current and VBB IEE Maximum Quiescent Supply Current without output termination currentg mA VEE pin
VBB Output reference voltage VCC - 1.4 VCC - 1.2 V IBB = 200 A a. Input have internal pullup/pulldown resistors which affect the input current b. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality c. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. d. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. e. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. f. Equivalent to a termination of 50W to VTT. g. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE ICC = (number of differential output pairs used) x (VOH - VTT)/Rload + (VOL - VTT)/Rload + IEE.
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Table 6. ECL DC Characteristics (VEE = -2.5V 5% or VEE = -3.3V 5%, VCC = GND, TJ = 0C to + 110C)
Symbol Control input CLK_SEL VIL VIH IIN Input voltage low Input voltage high Input Currenta -1.810 -1.165 -1.475 -0.880 100 V V A VIN = VIL or VIN = VIH Differential operation Differential operation VIN = VIL or VIN = VIH IOH = -30 mAd IOL = -5 mAd Characteristics Min Typ Max Unit Condition
Clock input pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP Differential input voltageb 0.1 VCMR IIN VOH VOL Differential cross point voltagec Input Currenta VEE + 1.0
1.3 -0.3 100
V V A
ECL clock outputs (Q0-9, Q0-9) Output High Voltage Output Low Voltage VEE = -3.3V5% VEE = -2.5V5% -1.2 -1.9 -1.9 -1.005 -1.705 -1.705 -0.7 -1.5 -1.3 V V
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Supply current and VBB IEE Maximum Quiescent Supply Current without output termination currente 100 mA VEE pin
VBB Output reference voltage VCC-1.4 VCC-1.2 V IBB = 200 A a. Input have internal pullup/pulldown resistors which affect the input current b. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality c. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. d. Equivalent to a termination of 50W to VTT. e. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE ICC = (number of differential output pairs used) x (VOH - VTT)/Rload + (VOL - VTT)/Rload + IEE.
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MC100ES6111
Table 7. AC Characteristics (ECL: VEE = -3.3V
Symbol Characteristics
5% or VEE = -2.5V 5%, VCC = GND) or (HSTL/PECL: VCC = 3.3V 5% or VCC = 2.5V 5%, VEE = GND, TJ = 0C to + 110C) a
Min Typ Max Unit Condition
Clock input pair CLKA, CLKA (PECL or ECL differential signals) VPP Differential input voltageb (peak-to-peak) VCMR fCLK tPD Differential input crosspoint voltagec PECL Input Frequencyd Propagation Delay CLKA or CLKB to Q0-9
0.15 VEE + 1.0 280 400
1.3 VCC - 0.3 2.7 530
V V GHz ps Differential Differential
Clock input pair CLKB, CLKB (HSTL differential signals) VDIF Differential input voltagee (peak-to-peak)e VX Differential input crosspoint voltagef Input Frequency Propagation Delay CLKB to Q0-9 fCLK tPD VO(P-P)
0.4 VEE + 0.68 280 400
1.0 VEE + 0.9 2.7 530
V V GHz ps Differential Differential
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ECL clock outputs (Q0-9, Q0-9) Differential output voltage (peak-to-peak) fO < 300 MHz fO < 1.5 GHz fO < 2.7 GHz Output-to-output skew Output-to-output skew (part-to-part) Output cycle-to-cycle jitter Output Pulse skewg TBD 75 ps 0.45 0.3 TBD 0.72 0.55 0.37 0.95 0.95 0.95 35 250 V V V ps ps Differential Differential
tsk(O) tsk(PP) tJIT(CC) tsk(P) a. b. c.
d. e. f.
g.
tr, tf Output Rise/Fall Time 0.05 0.3 ns 20% to 80% AC characteristics apply for parallel output termination of 50 to VTT VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew The MC100ES6111 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the V DIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
Differential Pulse Generator Z = 50W
ZO = 50
ZO = 50
RT = 50 VTT
DUT MC100ES6111
RT = 50 VTT
Figure 1. MC100ES6111 AC test reference
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MC100ES6111
APPLICATIONS INFORMATION
Understanding the junction temperature range of the MC100ES6111 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6111, the MC100ES6111 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this datasheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: Maintaining Lowest Device Skew The MC100ES6111 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6111 is a mixed analog/digital product. The differential architecture of the MC100ES6111 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
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TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 54.4 C/W (2s2p board, 200 ft/min airflow, see table 4) and a typical power consumption of 610 mW (all outputs terminated 50 ohms to VTT, VCC=3.3V, frequency independent), the junction temperature of the MC100ES6111 is approximately TA + 33 C, and the minimum ambient temperature in this example case calculates to -33 C (the maximum ambient temperature is 77 C. See Table 8). Exceeding the minimum junction temperature specification of the MC100ES6111 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6111 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 8: Ambient temperature ranges (Ptot = 610 mW)
Rthja (2s2p board) Natural convection 59.0 C/W 100 ft/min 200 ft/min 400 ft/min 800 ft/min 54.4 C/W 52.5 C/W 50.4 C/W 47.8 C/W TA, mina -36 C -33 C -32 C -30 C -29 C TA, max 74 C 77 C 78 C 79 C 81 C
VCC 33...100 nF 0.1 nF
VCC MC100ES6111
Figure 2. VCC Power Supply Bypass
a. The MC100ES6111 device function is guaranteed from TA=-40 C to TJ=110 C
TIMING SOLUTIONS
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MC100ES6111
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B
-U- V P AE
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B1
8
DETAIL Y
17
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
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GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
TIMING SOLUTIONS
-T-, -U-, -Z-
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NOTES
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MC100ES6111
NOTES
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TIMING SOLUTIONS
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MC100ES6111
NOTES
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MC100ES6111
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E Motorola, Inc. 2002.
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